`timescale 1ns/10ps
`define clock_period 20

module trist_driver_tb;

	reg data;
	reg enable;
	wire out;

	trist_driver trist0(
		.Data(data),
		.Enable(enable),
		.Out(out)
	);
	
	initial begin
		data = 1'b0;
		enable = 1'b0;
		#(`clock_period);//高阻输出
		
		enable = 1'b1;
		#(`clock_period);//输出0
		
		data = 1'b1;
		#(`clock_period);//输出1

	end
	
endmodule
